In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metalization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
During conductive interconnect manufacturing, a metal layer is deposited on the wafer. The deposited metal will fill regions on the wafer between smaller features, such as sub-micron features, faster than larger regions, such as trench regions. Because the smaller features may span relatively large areas of the wafer, it should be appreciated that these large areas of the wafer may have an increased topography. The increased topography regions need to be planarized in conjunction with planarization of the decreased topography regions. Simultaneous planarization of both the increased and decreased topography areas of the wafer poses a challenge. For example, to achieve sufficient planarization of the increased topography areas of the wafer, an extended overpolishing period may be required. However, exposure of the decreased topography areas of the wafer to this extended overpolishing period may cause removal of too much material from the decreased topography areas, e.g., the barrier layer underlying the deposited metal may be undesirably exposed and/or damaged.